Call for Papers




June 9-10, 2019, Rihga Royal Hotel Kyoto, Kyoto, Japan

(held prior to VLSI Technology Symposium, Satellite Workshop of VLSI Symposia)
Sponsored by
the Japan Society of Applied Physics and
the IEEE Electron Device Society

Deadline for Abstracts: March 15, 2019

Scope

The workshop will cover various aspects of VLSI-related silicon nanoelectronics. Areas of interest include, but are not limited to:

  • Sub-10 nm transistors employing conventional and novel architecture including non-classical structures, novel channel and source/drain materials, non-thermal injection mechanisms
  • Device physics of nanodevices including quantum effects, nonequilibrium and ballistic transport
  • Modeling and simulation of nanoscale devices
  • Extreme processing of nanostructures, including nanopatterning
  • Junction and insulator materials and process technology for nanodevices
  • Nanoscale surface, interface, and heterojunction effects in nanodevices
  • Device scaling issues including doping fluctuations and atomic granularity
  • Novel architectures for nanodevices including quantum computing
  • Optoelectronics using silicon nanostructures
  • Devices for heterogeneous integration on silicon, including 2D materials, Ge and III-V, CNT, spin-based devices, MEMs and NEMS, etc.
  • Environmental devices which contribute to low-carbon society (wireless sensors, energy harvestors, steep slope devices, etc.)

Submission of Abstract

Prospective authors are requested to submit an abstract of the original work. The abstract must be prepared as a PDF file and submitted ON-LINE at http://annex.jsap.or.jp/snw/ps.html

The abstract must consist of one page of text and one page of figures. The abstract must include the title, the author's names, affiliation, full address, phone and FAX numbers, and e-mail address. Faxed copies of the abstract will not be accepted. Accepted abstracts will be reproduced in the workbook exactly as received. The deadline for abstracts is March 15, 2019.

All accepted abstracts will be published in IEEE Xplore.

 Questions may be addressed to toshifumi1.irisawa[at]aist.go.jp (T. Irisawa). 

Further Information

Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2019 VLSI Technology Symposium. Some of the accepted papers will be presented in "Poster Sessions". Further information can be obtained at http://annex.jsap.or.jp/snw/