Kyushu Chapter, The Japan Society of Applied Physics

Logic device scaling imposes aggressive performance targets and stringent control on all involved processes. Amongst those, in situ epitaxy doping is a key step to reduce parasitic resistance in source/drain (S/D) - contact regions. For PMOS devices, active B doping concentrations ([B]_act) in selectively grown Si_1-xGe_x:B need to exceed 1 × 10²¹ cm^-3. This can be achieved with Ge contents in the 40% ≦ x ≦ 70% range. However, nanosheet (NS) devices and their stacking in complementary field effect transistor (CFET) introduce new challenges. S/D layers need to form laterally from {110}-oriented NS sidewalls with accurately controlled properties.

In this study, active and chemical B doping concentrations obtained on layers grown on Si(001), Si(110) and Si(111) were compared for selective and non-selective conventional processes. To make the process selective, addition of HCl in growth chemistry is required, unfortunately leading to a reduction in dopant incorporation. However, low temperature (LT) processes variant, relying on cyclic deposition-etch (CDE) routines, can be used to enable higher doping levels, while maintaining process selectivity.

In this context, we demonstrated the impact of substrate orientation on Si_1-xGe_x:B properties, revealing improved dopant incorporation and activation on Si(110) and Si(111) substrates using conventional processes. Additionally, a fully selective LT S/D process was successfully integrated into scaled NS and CFET structures, achieving high [B]_act, in the 〜1.5 × 10²¹ cm^-3 range as obtained for SiGe:B growth on Si(001).